Name: Silica
Author: simaanc

Silica MCP

RTL and FPGA tools: lint, simulate, formal, synthesize, place and route, program a board.

Grade A Local · stdio No auth needed 18 tools v0.5.0 AGPL-3.0

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93/100

trust score

tools declared

local

runs on your machine

—

downloads a day

What it does

RTL and FPGA tools: lint, simulate, formal, synthesize, place and route, program a board.

Quickstart

# 1 — add it to Claude Code
claude mcp add --scope user silica-mcp '--' uvx silica-eda

# 2 — ask your agent for something these tools do
#   run_cocotb, read_coverage, doctor and 15 more

Silica costs nothing on mcprush: there is no plan to choose here, no cap to set and nothing mcprush can bill you for.

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Tool surface

What the model actually sees. Descriptions are diffed on every release — see version history.

Only tools that write or reach the network

Read from its source code. A server that builds its tool list when it starts can list more tools than this.

Run a cocotb (Python) testbench against an HDL design.

Parameter	Type	Required	Notes
sources	array	yes	HDL design files. May include `.f` filelists (one path per line), expanded in place.
test_module	string	yes	Path to the Python cocotb test file (contains the @cocotb.test() coroutines).
toplevel	string	yes	Top-level HDL module cocotb instantiates.
simulator	string	no	"icarus" \| "verilator" \| "ghdl" \| "questa" \| "xcelium" \| "vcs". Icarus is the most common cocotb pairing.
timeout	integer	no	Seconds before killing the build+test run.

Summarize a Verilator coverage.dat as structured line coverage.

Parameter	Type	Required	Notes
coverage_dat	string	yes	Path to the coverage.dat produced by a coverage run (the run_simulation result's coverage_dat field).
max_uncovered	integer	no	Cap on uncovered line numbers reported per file; "uncovered_truncated" is set when the cap is hit.
timeout	integer	no	Seconds before killing verilator_coverage.

Report silica's version and which EDA tools it can use, with a fix for each gap.

Parameter	Type	Required	Notes
check_updates	boolean	no	Also ask PyPI (3 s timeout) whether a newer silica-eda exists. Offline or blocked networks just report the check as unavailable. Set SILICA_NO_UPDATE_CHECK=1 to skip it everywhere.

Run formal verification or equivalence checking and return structured results.

Parameter	Type	Required	Notes
sby_file	string	no	Path to an existing config file (.sby, .eqy, or .tcl).
files	array	no	RTL source files for property verification (when sby_file is omitted).
top	string	no	Top module name.
mode	string	no	"prove" \| "bmc" \| "cover" \| "live". Default: "prove". (sby only)
depth	integer	no	Bound depth for bmc/prove. Default: 20. (sby only)
engine	string	no	"auto" or explicit e.g. "smtbmc z3". (sby only)
tool	string	no	"auto" \| "sby" \| "eqy" \| "jaspergold" \| "vc_formal". Auto uses config priority order.
timeout	integer	no	Seconds before killing the tool. Default: 300.
gold_files	array	no	Gold (reference) design files for equivalence checking (eqy only).
gate_files	array	no	Gate (implementation) design files for equivalence checking (eqy only).

Auto-format a SystemVerilog/Verilog file and return a unified diff.

Parameter	Type	Required	Notes
file	string	yes	Path to the source file to format.
dry_run	boolean	no	If True (default), return the diff without writing. If False, overwrite the file with the formatted output.
tool	string	no	"auto" \| "verible". Auto uses config priority order.
timeout	integer	no	Seconds before killing the formatter.

Lint a SystemVerilog/Verilog file and return structured warnings.

Parameter	Type	Required	Notes
file	string	yes	Path to the source file to lint. May instead be a `.f` filelist (one path per line); each listed file is linted.
ruleset	string	no	"default" \| "all" \| comma-separated rule list (tool-specific).
tool	string	no	"auto" \| "verible" \| "verilator" \| "svlint" \| "spyglass". Auto uses config priority order.
timeout	integer	no	Seconds before killing the linter (applied per file).
extra_files	array	no	Additional files to lint. Each may itself be a `.f` filelist, expanded in place. Warnings across all files are merged into one result. Verilator elaborates all the files together, so pass a design's

Place and route an FPGA netlist and return timing and utilization.

Parameter	Type	Required	Notes
netlist	string	yes	Path to Yosys JSON netlist (produced by the synthesize tool).
arch	string	no	FPGA architecture — "ice40" \| "ecp5" \| "nexus" \| "machxo2" \| "generic" \| "xilinx".
device	string	no	Device variant within the architecture: ice40: "hx1k" \| "hx4k" \| "hx8k" \| "up5k" \| "lp1k" \| "lp8k" \| ... ecp5: "LFE5U-12F" \| "LFE5U-25F" \| "LFE5U-45F" \| "LFE5U-85F", also LFE5UM-/LFE5UM5G- parts; a s
package	string	no	Package code, e.g. "ct256" (ice40), "CABGA381" (ecp5). Optional.
constraint	string	no	Path to physical constraint file (.pcf for ice40, .lpf for ecp5, .xdc for xilinx).
output	string	no	Output file path for the bitstream. Auto-placed in temp dir if omitted — the path is returned in the result. A path ending in .asc/.textcfg/.fasm keeps nextpnr's file there and writes the bitstream be
freq	number	no	Target clock frequency in MHz for timing checks.
tool	string	no	"auto" \| "nextpnr". Auto uses config priority order.
timeout	integer	no	Seconds before killing the tool.

Program a bitstream to an FPGA device with openFPGALoader.

Parameter	Type	Required	Notes
bitstream	string	yes	Path to a loadable bitstream from run_place_route: .bit (Xilinx, ECP5) or .bin (iCE40). nextpnr's .asc/.textcfg text configs can't be loaded directly.
board	string	no	Board preset name, e.g. "arty_a7_100t", "arty_a7_35t", "basys3", "cmod_a7", "nexys4ddr", "ice40_hx8k_b_evn". Plain "arty" is the 35T. Run openFPGALoader --list-boards for all.
cable	string	no	JTAG cable, e.g. "ft2232", "digilent_hs2", "jlink", "olimex". Run openFPGALoader --list-cables for all options.
device	string	no	Explicit FPGA part number override, e.g. "xc7a35t". Optional.
spi_flash	boolean	no	When True, program SPI flash (persistent across power cycles), replacing whatever design the board boots. Only do this when the user asks. Default False: SRAM (volatile, erased on power cycle).
tool	string	no	"auto" \| "openfpgaloader". Auto uses config priority order.
timeout	integer	no	Seconds before killing the programmer.

List the project's RTL and constraint files.

Parameter	Type	Required	Notes
root	string	no	Directory to scan, inside the project (defaults to the project root).

Read an RTL file, optionally restricted to a line range.

Parameter	Type	Required	Notes
file	string	yes	Path to the file; must stay inside the project directory.
start_line	integer	no	First line to return (1-indexed, inclusive).
end_line	integer	no	Last line to return (1-indexed, inclusive).

Write (or diff) proposed RTL content to a file.

Parameter	Type	Required	Notes
file	string	yes	Path to the target file; must stay inside the project directory.
content	string	yes	Complete new file content.
dry_run	boolean	no	If True (default), return a unified diff without writing. If False, write.

Grep across project RTL files with surrounding context.

Parameter	Type	Required	Notes
query	string	yes	Search string (literal, not regex).
root	string	no	Directory to search, inside the project (defaults to the project root).
scope	string	no	"all" \| "sv" \| "v" — filter by file extension.

Read and return the content of a constraint file (.xdc / .sdc / .lpf / .upf).

Parameter	Type	Required	Notes
file	string	yes	Path to the constraint file; must stay inside the project directory.

Capture a board's UART output, optionally sending text first.

Parameter	Type	Required	Notes
port	string	yes	Serial device to open, e.g. "/dev/ttyUSB1" or "/dev/serial/by-id/usb-...-if01-port0" (Linux), "COM4" (Windows). On boards with an FTDI JTAG+UART bridge the UART is usually the second interface (if01).
baud	integer	no	Baud rate; 8N1, no flow control.
duration	number	no	Seconds to listen (at most 600).
send	string	no	Text to write once send_delay has passed, e.g. "hello\\r".
send_delay	number	no	Seconds to listen before sending.
expect	string	no	Regex searched for in the captured text, e.g. "Silica .* SoC".
stop_on_match	boolean	no	Stop as soon as expect matches (default) instead of listening for the full duration.

Run RTL simulation and return structured diagnostics.

Parameter	Type	Required	Notes
file	string	yes	Path to the DUT source file (.sv / .v for Verilog, .vhd for VHDL). May instead be a `.f` filelist (one source path per line); its entries become the design sources.
testbench	string	yes	Path to the testbench file.
simulator	string	no	"auto" \| "verilator" \| "icarus" \| "iverilog" \| "ghdl" \| "vcs" \| "questa" \| "xcelium". "iverilog" is accepted as an alias for "icarus". Auto uses config priority order.
top	string	no	Top module/entity name (inferred from testbench filename if omitted).
timeout	integer	no	Seconds before killing the simulator process.
trace	boolean	no	When True, collect the VCD the testbench writes (it must call $dumpfile/$dumpvars) into a persistent directory and return its path as trace_vcd. Read it with read_waveform, or open it with launch_wave
extra_sources	array	no	Additional design files (submodules, packages) compiled alongside the DUT. Each entry may itself be a `.f` filelist, which is expanded in place.
coverage	boolean	no	When True, collect line/toggle coverage (Verilator only). Returns coverage_dat in the result — pass it to read_coverage for a structured report.

Synthesize RTL and return structured utilization and timing summary.

Parameter	Type	Required	Notes
top_module	string	yes	Name of the top-level module to synthesize.
files	array	yes	List of source file paths (.sv / .v).
target	string	no	Synthesis target. Yosys: "generic" \| "ice40" \| "ecp5" \| "xilinx" \| "gowin" Vivado: FPGA part string e.g. "xc7a35tcsg324-1", or shorthand "artix7" \| "kintex7" \| "ultrascale" \| "ultrascale+" \| "zynq"
tool	string	no	"auto" \| "yosys" \| "vivado" \| "quartus" \| "dc_shell". Auto uses config priority order.
timeout	integer	no	Seconds before killing the synthesis process.

Open a VCD/FST/FSDB trace file in a waveform viewer (fire-and-forget).

Parameter	Type	Required	Notes
trace_file	string	yes	Absolute path to the .vcd, .fst, or .fsdb trace file.
viewer	string	no	"auto" \| "surfer" \| "gtkwave" \| "verdi". Auto picks from config priority order.

Read signal values from a VCD or FST trace — no viewer needed.

Parameter	Type	Required	Notes
trace_file	string	yes	Path to the trace. VCD is read directly; .fst is converted via the OSS CAD Suite's fst2vcd first.
signals	array	no	Signal names to read. A name matches on the full hierarchical path ("tb.dut.count") or any trailing component ("count", "dut.count"). Omit to list the signals available in the trace instead.
time_start	integer	no	Window start in VCD ticks (multiply timescale to get time). Each signal's value just before the window is included so state at window start is known.
time_end	integer	no	Window end in VCD ticks.
max_transitions	integer	no	Per-signal cap; "truncated" is set when hit.

Free

$0 forever

Every tool, no call limit
No card, and mcprush charges nothing for it
Source published under AGPL-3.0
Runs on your machine — nothing of it reaches our gateway
Nothing to cap, because mcprush bills nothing

Nothing here is billable: mcprush charges nothing to install Silica or to call it, at any volume.

ATrust score 93 / 100

Release 0.5.0 · scanned 28 Oct 2026

Two independent axes, because powerful and malicious are different questions. The grade is threat only. The capability level is blast radius, and it is never a penalty on the grade — it is priced as one subtract-only term in the score, where you can see it.

Threat score100

Client score93

Findings10 threat · 0 capability

Capabilityhigh

Coveragesource

Verificationrepo

Surface digestb4e1070a00044f1c275d449f9248aec263f0a194dae1fb146c8fb485457bacd8

Score vectorthreat 100 → client 93

Term	Level	What it prices	Points
capability-exposure	high	capability blast radius (high) — client exposure if the model is manipulated	−6
verification-discount	repo	publisher verification (public source) — no provenance, but the source is public and inspectable	−1
coverage-honesty	source	inspection depth (source) — how much of the target the scan could see	−0

score = clamp(round(threatScore − E_cap − E_ver − E_cov), 0, 100). No model, no opinion, no network call at scoring time: the same methodology version against the same bytes always produces this number, and every line above is a field of the report rather than a summary of it.

What the scan could actually read

A grade is only as meaningful as its coverage, so the scanner publishes its own depth before it publishes its result.

Tool surfaceread

Implementation sourceread

Package metadataread

Live transportnot available

Tools were statically extracted from the published source (18 recovered), not enumerated from a running server. Tool-poisoning, Unicode-smuggling, capability and toxic-flow analysis ran on this inferred surface, but a mis-parsed registration could be missed or mis-attributed, so tool-derived findings are capped below “confirmed”. To grade the real runtime surface, scan the running server: --command "npx -y <package>".

Capability — what it could do if the model were manipulated

Tags derived from each tool’s schema and the implementation, not from what the tool calls itself. high is the level these add up to.

Tool	Capability tags	Why the tag was assigned
run_cocotb	no tags
read_coverage	no tags
doctor	no tags
run_formal	no tags
format_rtl	no tags
lint	no tags
run_place_route	no tags
program_device	no tags
get_project_structure	no tags
read_rtl	no tags
write_rtl	no tags
search_rtl	no tags
get_constraints	no tags
capture_serial	no tags
run_simulation	no tags
synthesize	no tags
launch_waveform	no tags
read_waveform	no tags

Toxic-flow graph

The lethal trifecta, checked as a graph rather than as a checklist: untrusted input, a sensitive source and an external sink have to meet before there is a path worth worrying about.

The public result for this release does not print the flow graph, so there is nothing to show here. That is not the same as "no paths were found": what the scan did read is above, under coverage.

Supply chain and provenance

Integrityfirst-seen

Surface digestb4e1070a00044f1c

Scanned2026-10-28

This is the first scan of this surface here, so there is nothing yet to compare it against.

Every result on this tab comes from one deterministic pass over the published package — offline, rule by rule, and auditable line by line above. Same methodology version, same bytes, same score.

Where are you running it?

Tool surface

Release history

Silica MCP

What it does

Quickstart

Where are you running it?

Tool surface

What counts against your monthly calls

What the scan could actually read

Capability — what it could do if the model were manipulated

Toxic-flow graph

Supply chain and provenance

Release history

See also