Name: Vivado Red
Author: sinemortal

Vivado Red MCP

Drive AMD Vivado from AI assistants, with Red Pitaya STEMlab 125-14 build and deploy flows.

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What it does

Drive AMD Vivado from AI assistants, with Red Pitaya STEMlab 125-14 build and deploy flows.

Quickstart

# 1 — add it to Claude Code
claude mcp add --scope user vivado-red-mcp '--' uvx vivado-red-mcp

# 2 — ask your agent for something these tools do
#   create_block_design, save_bd_design, close_bd_design and 90 more

Vivado Red costs nothing on mcprush: there is no plan to choose here, no cap to set and nothing mcprush can bill you for.

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Tool surface

What the model actually sees. Descriptions are diffed on every release — see version history.

Only tools that write or reach the network

Read from its source code. A server that builds its tool list when it starts can list more tools than this.

Create a new block design and make it current. Optionally sets the board_part property on the project beforehand (board_part requires the BSP to be installed in Vivado).

Parameter	Type	Required	Notes
name	string	yes	Block design name (no .bd)
board_part	string	no	Optional vendor:board:part string (e.g. 'digilentinc.com:arty-a7-35:part0:1.0')

Save the currently open block design to disk.

No parameter schema on file.

Close the currently open block design (without deleting).

No parameter schema on file.

List cells in the current block design (optionally filtered).

Parameter	Type	Required	Notes
filter	string	no	Wildcard pattern, default '*'

Add an IP core to the current block design (create_bd_cell -type ip -vlnv ...). If config is provided, the CONFIG.* keys are applied via set_property -dict.

Parameter	Type	Required	Notes
cell_name	string	yes	Instance name (e.g. 'processing_system7_0')
vlnv	string	yes	Vendor:Library:Name:Version (e.g. 'xilinx.com:ip:processing_system7:5.5')
config	object	no	Dict of CONFIG.* properties (e.g. {'CONFIG.PCW_USE_M_AXI_GP0': '1'})

Create a top-level port on the current block design. Scalar or vector (from/to) via create_bd_port, or an interface port when vlnv is given (create_bd_intf_port, e.g. the XADC 'xilinx.com:interface:diff_analog_io_rtl:1.0'). Port names must match the constraints (XDC) of the board.

Parameter	Type	Required	Notes
name	string	yes	Port name (e.g. 'led_o')
direction	string	no	Direction for a plain port (default: I)
from	integer	no	MSB index for a vector port (e.g. 7)
to	integer	no	LSB index for a vector port (default: 0)
type	string	no	Optional port type: clk, rst, ce, intr, data, undef
vlnv	string	no	Interface VLNV: creates an interface port instead
mode	string	no	Interface mode (default: Slave): Master, Slave, ...

Add an RTL module (Verilog/VHDL already in the project, see add_sources) to the current block design as a module-reference cell (create_bd_cell -type module -reference). Optional config sets its parameters, e.g. {'CONFIG.WIDTH': '8'}; string parameters keep their quotes, e.g. {'CONFIG.init':…

Parameter	Type	Required	Notes
module	string	yes	Top module name of the RTL
cell_name	string	yes	Instance name in the BD
config	object	no	Dict of CONFIG.* parameters

Set CONFIG.* properties on an existing block-design cell (set_property -dict). Use for settings that must be applied after creation or in a separate step, e.g. importing a PS7 board preset: {'CONFIG.PCW_IMPORT_BOARD_PRESET': '<path>/red_pitaya.xml'}.

Parameter	Type	Required	Notes
cell_name	string	yes	—
config	object	yes	Dict of CONFIG.* properties

Connect two scalar pins/ports in the current block design.

Parameter	Type	Required	Notes
pin_from	string	yes	e.g. 'processing_system7_0/FCLK_CLK0'
pin_to	string	yes	e.g. 'axi_gpio_0/s_axi_aclk'

Connect two AXI/interface pins in the current block design.

Parameter	Type	Required	Notes
intf_from	string	yes	e.g. 'processing_system7_0/M_AXI_GP0'
intf_to	string	yes	e.g. 'axi_gpio_0/S_AXI'

Use apply_bd_automation -rule xilinx.com:bd_rule:axi4 to wire an AXI master to a slave (inserts AXI interconnect + clock/reset hookups).

Parameter	Type	Required	Notes
master	string	yes	AXI master intf pin
slave	string	yes	AXI slave intf pin
options	object	no	Optional extra -config key/value pairs (e.g. {'Clk_master': 'Auto'})

Apply the Zynq-7000 processing_system7 board preset to a PS7 cell — wires FIXED_IO / DDR / clocks per the board definition. Equivalent to clicking 'Run Block Automation' on a freshly added PS7 in the GUI.

Parameter	Type	Required	Notes
cell	string	no	PS7 cell name (default: 'processing_system7_0')
apply_board_preset	boolean	no	Whether to apply the current board preset (default: true)

Run validate_bd_design and return parsed status. Failures include unconnected pins, conflicting CONFIG values, or missing assignments.

No parameter schema on file.

Regenerate the block design layout (cosmetic; useful before save).

No parameter schema on file.

Auto-assign addresses in the BD address editor (assign_bd_address).

No parameter schema on file.

Generate the HDL wrapper for a block design and (by default) add it to sources_1 and set it as project top. Implements the canonical pattern: make_wrapper -files <bd> -top; add_files -norecurse <wrapper>; set_property top <wrapper> [current_fileset]; update_compile_order.

Parameter	Type	Required	Notes
bd_name	string	yes	Block design name (no .bd)
set_top	boolean	no	Also set the wrapper as project top (default: true)

Download the RedPitaya-FPGA repo from GitHub as a source zip and extract it (no git required, stdlib only). Returns repo_path to feed into rp_setup_workspace. Idempotent — pass force=true to redownload. No Vivado session required.

Parameter	Type	Required	Notes
dest_path	string	no	Directory to extract into. Default: current working directory.
ref	string	no	Branch or tag to fetch (default: master). Extracted dir is RedPitaya-FPGA-<ref>.
url	string	no	Override the full zip URL (e.g. a tag or a fork). If set, ref is used only for the expected dir name.
force	boolean	no	If true, delete an existing extracted dir and redownload (default: false).
timeout	integer	no	Download timeout in seconds (default: 600).

Copy a RedPitaya-FPGA repo into an isolated workspace so builds don't touch the pristine checkout. The copy is patched to run on the installed Vivado release (block-design version check) and without git. Idempotent — pass force=true to recopy. No Vivado session required.

Parameter	Type	Required	Notes
repo_path	string	yes	Path to the RedPitaya-FPGA checkout (contains prj/, rtl/, brd/, *.tcl)
workspace_path	string	no	Destination workspace dir. Default: <repo_parent>/redpitaya_mcp_workspace
force	boolean	no	If true, delete and recopy an existing workspace (default: false)

List projects under prj/ of a RedPitaya workspace or repo. Flags which are Z10-capable (have ip/system.tcl or legacy ip/systemZ10.tcl). No Vivado session required.

Parameter	Type	Required	Notes
path	string	yes	Workspace or repo root (the dir that contains prj/)

Report workspace state: projects present and which already have a built bitstream.

Parameter	Type	Required	Notes
workspace_path	string	yes	—

Clone an existing prj/<base> into prj/<name> inside the workspace, ready for custom PL logic. Returns the rtl/ dir and red_pitaya_top path to edit. No Vivado session required.

Parameter	Type	Required	Notes
workspace_path	string	yes	—
base_project	string	yes	Existing project to clone (e.g. 'v0.94', 'barebones')
name	string	yes	New project name

Build a RedPitaya PS+PL project end-to-end: run the repo's project setup TCL (creates the PS7 block design from ip/system.tcl), then synthesis, implementation and write_bitstream, then generate the .bit.bin. Returns {stage, xpr_path, bit_path, bin_path, timing}. Requires start_session first.

Parameter	Type	Required	Notes
workspace_path	string	yes	—
project	string	yes	Project under prj/ to build (e.g. 'v0.94', 'barebones')
model	string	no	Board model — only 'Z10' supported (default: Z10)
defines	string	no	Extra Verilog defines passed as tclarg 1 (default: empty)
jobs	integer	no	Parallel jobs for synth/impl (default: 4)
setup_timeout	integer	no	Project-setup TCL timeout s (default: 900)
synth_timeout	integer	no	Synthesis timeout s (default: 2400)
impl_timeout	integer	no	Implementation timeout s (default: 5400)
synth_flags	string	no	Extra synth_design flags via STEPS.SYNTH_DESIGN.ARGS.MORE_OPTIONS. Default empty. RedPitaya canonical for reproducibility: '-flatten_hierarchy none -bufg 16 -keep_equivalent_registers' (NOTE: those pr

Run report_power and return parsed totals (total/dynamic/static W) + a truncated raw block. Full output stored at /tmp/vivado_red_mcp/.

No parameter schema on file.

Run report_drc and return parsed violations list (severity/code/message). Use after place_design/route_design to catch design-rule problems.

No parameter schema on file.

Run report_methodology (UltraFast methodology checks). Returns violation list grouped by severity.

No parameter schema on file.

Run report_qor_assessment (overall design quality score).

No parameter schema on file.

Run report_clock_interaction to find cross-clock paths (timed/async/unconstrained).

No parameter schema on file.

Get timing summary (WNS, TNS, WHS, THS). Returns parsed metrics by default. Use generate_full_report for raw output.

Parameter	Type	Required	Notes
report_type	string	no	summary (default), setup, hold, or all
detail_level	string	no	summary \| standard (+ truncated raw) \| full (+ complete raw)

Get failing/critical timing paths. Returns structured summary by default; use detail_level=standard|full for the raw text too.

Parameter	Type	Required	Notes
num_paths	integer	no	Number of paths (default: 10)
slack_threshold	number	no	Only show paths with slack < this (default: 0 = failing paths)
path_type	string	no	setup (default) or hold
from_pin	string	no	Filter -from pattern
to_pin	string	no	Filter -to pattern
through	string	no	Filter -through pattern
clock	string	no	Filter by clock domain
detail_level	string	no	summary (default) \| standard \| full

Resource utilization (LUT/FF/BRAM/DSP/IO). Parsed only by default.

Parameter	Type	Required	Notes
hierarchical	boolean	no	Hierarchical breakdown (default: false)
detail_level	string	no	—
module_filter	string	no	Wildcard for hierarchical filter
threshold_percent	number	no	Mark resources below this util%% as below_threshold

Get clock information and constraints (report_clocks).

No parameter schema on file.

Get Vivado messages filtered by severity (error/critical/warning/all).

Parameter	Type	Required	Notes
severity	string	no	all (default) \| error \| critical \| warning

Copy a .bit.bin to a Red Pitaya over SSH/SCP and load it into the FPGA. Uses /dev/xdevcfg (works on Red Pitaya OS 1.04 + 2.00) or fpgautil (OS 2.00). No Vivado session required.

Parameter	Type	Required	Notes
bit_bin_path	string	yes	Absolute path to the local .bit.bin produced by generate_cfgmem
host	string	yes	Red Pitaya IP or hostname (e.g. '192.168.1.100' or 'rp-f0abcd.local')
user	string	no	SSH user (default: 'root')
password	string	no	SSH password (default: 'root' — Red Pitaya factory default)
key_filename	string	no	Path to an SSH private key. If set, overrides password auth.
port	integer	no	SSH port (default: 22)
remote_path	string	no	Remote .bit.bin path (default: /tmp/<basename>)
method	string	no	Loader: 'xdevcfg' (default, both OS) or 'fpgautil' (OS 2.00)
connect_timeout	integer	no	SSH connect timeout in seconds (default: 10)
keep_remote	boolean	no	Leave the .bit.bin on the board after loading (default: false → rm)

Run an arbitrary shell command on a Red Pitaya over SSH and return stdout/stderr/exit code. Useful for status checks, dmesg reads, manual loader invocations.

Parameter	Type	Required	Notes
host	string	yes	—
command	string	yes	Shell command to execute
user	string	no	—
password	string	no	—
key_filename	string	no	—
port	integer	no	—
connect_timeout	integer	no	—
exec_timeout	integer	no	Command timeout (default: 30s)

Get the design hierarchy (modules and instances), optionally filtered.

Parameter	Type	Required	Notes
max_depth	integer	no	Max hierarchy depth (default: 3)
instance_pattern	string	no	Wildcard pattern (e.g., 'cpu', 'core/alu/*')

Get top-level I/O ports of the design.

No parameter schema on file.

Search for nets by pattern (default '*').

Parameter	Type	Required	Notes
pattern	string	no	Wildcard pattern (default: '*')
limit	integer	no	Max results (default: 100)

Search for cells/instances by pattern.

Parameter	Type	Required	Notes
pattern	string	no	Wildcard pattern (default: '*')
limit	integer	no	Max results (default: 100)

Look up a topical Vivado documentation summary bundled with this server. Returns markdown content + upstream URL. Known topics: block_design, ps7_zynq, timing_constraints, synthesis_strategies, simulation_xsim, red_pitaya_125_14, redpitaya_ps_pl_flow, tcl_quoting, hw_manager, ip_integrator,…

Parameter	Type	Required	Notes
topic	string	yes	Topic name; see KNOWN_TOPICS in the tool description
version	string	no	Target Vivado version (cosmetic, default '2020.1')

List the bundled Vivado documentation topics.

No parameter schema on file.

Submit a feature request for the Vivado MCP server (persisted on disk).

Parameter	Type	Required	Notes
title	string	yes	Short title
description	string	yes	What you need and why
use_case	string	no	Task that prompted the request
priority	string	no	—

List all submitted feature requests.

No parameter schema on file.

Run synthesis on the current project (reset_run -> launch_runs synth_1 -> wait_on_run). Returns ground-truth status from the run object, not just text parsing.

Parameter	Type	Required	Notes
jobs	integer	no	Parallel jobs (default: 4)
timeout	integer	no	Timeout seconds (default: 2400 = 40min). Increase for large designs.

Run implementation (opt_design -> place_design -> route_design). Returns ground-truth status from the impl_1 run object.

Parameter	Type	Required	Notes
jobs	integer	no	Parallel jobs (default: 4)
timeout	integer	no	Timeout seconds (default: 5400 = 90min).

Generate bitstream — launch_runs impl_1 -to_step write_bitstream -> wait_on_run. Returns ground-truth run status and the .bit path.

Parameter	Type	Required	Notes
timeout	integer	no	Timeout in seconds (default: 3600)

Set the strategy of a synthesis or implementation run (e.g. synth_1 'Flow_PerfOptimized_high', impl_1 'Performance_NetDelay_high'). On an unknown name, Vivado's error lists the valid strategies.

Parameter	Type	Required	Notes
run	string	yes	Run name (e.g. synth_1, impl_1)
strategy	string	yes	Strategy name

Open the Hardware Manager (no JTAG connection yet).

No parameter schema on file.

Close the Hardware Manager.

No parameter schema on file.

Connect to a hw_server (cs_server). Default URL is localhost:3121 — the value Vivado uses when running hw_server locally.

Parameter	Type	Required	Notes
url	string	no	host:port (default: localhost:3121)

Refresh the currently selected hardware device (re-reads JTAG chain state). Call after re-plugging a cable.

No parameter schema on file.

Program a .bit onto the first device on the JTAG chain. Sequence: open_hw_target -> set PROGRAM.FILE -> program_hw_devices. The hardware must already be connected (open_hw_manager + connect_hw_server).

Parameter	Type	Required	Notes
bit_file	string	yes	Absolute path to .bit
probes_file	string	no	Optional ILA probes .ltx file

Create an IP from the Xilinx IP catalog. Generates a .xci file in the project's IP sources fileset. Use configure_ip + generate_ip_target afterwards, then run synth_ip if you want out-of-context synthesis.

Parameter	Type	Required	Notes
ip_name	string	yes	Catalog name (e.g. 'clk_wiz')
module_name	string	yes	Instance/module name on disk (e.g. 'clk_wiz_0')
vendor	string	no	default: xilinx.com
library	string	no	default: ip
version	string	no	Optional explicit version

Set CONFIG.* properties on an existing IP via set_property -dict.

Parameter	Type	Required	Notes
module_name	string	yes	—
config	object	yes	Dict of CONFIG.* keys to values (e.g. {'CONFIG.PRIM_IN_FREQ': '125'})

Generate IP output products (synthesis + simulation by default).

Parameter	Type	Required	Notes
module_name	string	yes	—
targets	array	no	default: ['synthesis', 'simulation']

Run out-of-context (OOC) synthesis on an IP.

Parameter	Type	Required	Notes
module_name	string	yes	—

Upgrade IP version (no-op if already at latest).

Parameter	Type	Required	Notes
module_name	string	no	Specific IP to upgrade; if omitted, upgrades all in project

Get a structured snapshot of the project's IP and their upgrade status.

No parameter schema on file.

Open an existing Vivado project (.xpr file).

Parameter	Type	Required	Notes
project_path	string	yes	Path to .xpr project file

Close the currently open project.

No parameter schema on file.

Get name, part, target language, directory of the open project.

No parameter schema on file.

Create a new Vivado project on disk in project mode. Defaults to the Red Pitaya STEMlab 125-14 part (xc7z010clg400-1). Call add_sources / add_constraints next, then run_synthesis.

Parameter	Type	Required	Notes
name	string	yes	Project name
directory	string	yes	Parent directory; project created at <directory>/<name>
part	string	no	Xilinx part number (default: {DEFAULT_PART})
force	boolean	no	Overwrite existing project (default: true)
target_language	string	no	Verilog or VHDL (default: Verilog)

Add HDL source files (.v/.sv/.vhd) to the current project. Optionally sets the top module and updates compile order.

Parameter	Type	Required	Notes
files	array	yes	Absolute paths to HDL source files
fileset	string	no	Target fileset (default: sources_1)
set_top	string	no	If given, set this module as project top after adding files

Add XDC constraint files to the current project.

Parameter	Type	Required	Notes
files	array	yes	Absolute paths to .xdc files
fileset	string	no	Target fileset (default: constrs_1)

List boards with bundled XDC + metadata. No Vivado session required.

No parameter schema on file.

Get bundled metadata for a board: part, LED pinout, absolute XDC paths, default synth flags. Use the returned absolute_path values with add_constraints. No Vivado session required.

Parameter	Type	Required	Notes
board	string	yes	Board identifier, e.g. 'red_pitaya_125_14'

Resolve a bundled board XDC and attach it to the current project. Standalone wrapper over get_board_info + add_constraints.

Parameter	Type	Required	Notes
board	string	yes	Board id, e.g. 'red_pitaya_125_14'
variant	string	no	XDC variant id (e.g. 'leds_min', 'full'). Default: 'full'

Convert a .bit into a raw binary image (.bit.bin) loadable via /dev/xdevcfg on the Red Pitaya. Use after generate_bitstream.

Parameter	Type	Required	Notes
bit_file	string	yes	Absolute path to input .bit
output	string	no	Output .bit.bin path (default: <bit_file>.bin)

Return structured errors and critical warnings from a run's log (default: synth_1), plus those of every failed run (e.g. out-of-context IP runs). Use after run_synthesis fails to get a clean actionable list.

Parameter	Type	Required	Notes
run	string	no	default: synth_1
max_items	integer	no	default: 50

One-shot composite: create project -> add HDL sources -> apply XDC -> synth -> impl -> write_bitstream -> generate .bit.bin. Stops on the first failing stage and returns a structured payload.

Parameter	Type	Required	Notes
name	string	yes	—
directory	string	yes	—
verilog_files	array	yes	—
top_module	string	yes	—
board	string	no	default: red_pitaya_125_14
xdc_variant	string	no	—
extra_xdc_files	array	no	—
synth_flags	string	no	—
jobs	integer	no	—
synth_timeout	integer	no	—
impl_timeout	integer	no	—

Generate a full Vivado report to a file. Use when inline reports get truncated or you need the complete output. Returns a report_id usable with read_report_section.

Parameter	Type	Required	Notes
report_type	string	yes	—
options	object	no	Report-specific options (e.g. {hierarchical: true})
output_file	string	no	Optional custom output path

Read a section of a previously generated report. Provide report_id (from generate_full_report) or a direct file_path.

Parameter	Type	Required	Notes
report_id	string	no	—
file_path	string	no	—
start_line	integer	no	1-indexed (default: 1)
num_lines	integer	no	default: 100
search_pattern	string	no	Regex to locate a section; returns context around first match

Start a persistent Vivado TCL session. Must be called before project/design tools. Vivado startup is ~30s; the session is reused across tool calls.

Parameter	Type	Required	Notes
vivado_path	string	no	Path to vivado(.bat) executable (default: 'vivado' from PATH).

Stop the Vivado TCL session and free resources.

No parameter schema on file.

Get statistics for the current Vivado session (commands run, timing, errors).

No parameter schema on file.

Verify the Vivado process is responsive. With auto_recover=true the session is restarted if it hangs.

Parameter	Type	Required	Notes
auto_recover	boolean	no	Restart session if unhealthy (default: true)

Get host hostname, free memory, and session state. Useful to check there is enough RAM before launching synthesis/implementation.

No parameter schema on file.

Launch xsim in behavioral/post-synth/post-impl mode.

Parameter	Type	Required	Notes
mode	string	no	Simulation mode (default: behavioral)

Run the simulation for a specified time (e.g. 100ns, 1us, all).

Parameter	Type	Required	Notes
time	string	yes	100ns \| 1us \| 10ms \| all

Restart the simulation from time 0.

No parameter schema on file.

Close the current simulation.

No parameter schema on file.

Get the current simulation time (current_time).

No parameter schema on file.

Get current value of a signal in simulation.

Parameter	Type	Required	Notes
signal	string	yes	Hierarchical signal path
radix	string	no	Display radix (default: hex)

Get values of multiple signals matching a wildcard pattern (max 50).

Parameter	Type	Required	Notes
pattern	string	yes	Signal pattern, e.g. /tb/dut/*
radix	string	no	—

Add signals to the waveform viewer.

Parameter	Type	Required	Notes
signals	array	yes	—

Set the top-level testbench module for simulation.

Parameter	Type	Required	Notes
top_module	string	yes	—
fileset	string	no	default: sim_1

List simulation objects in a scope (signals/ports/internal).

Parameter	Type	Required	Notes
scope	string	no	default: /
filter	string	no	—

List child scopes (hierarchy) in the simulation.

Parameter	Type	Required	Notes
parent	string	no	default: /

Step simulation by delta cycles.

Parameter	Type	Required	Notes
count	integer	no	default: 1

Add a breakpoint on signal edge or change.

Parameter	Type	Required	Notes
signal	string	yes	—
condition	string	no	—

Remove all breakpoints (remove_bps -all).

No parameter schema on file.

Get simulation log messages filtered by severity.

Parameter	Type	Required	Notes
severity	string	no	—

Execute a raw TCL command in Vivado. Use for advanced ops not covered by other tools.

Parameter	Type	Required	Notes
command	string	yes	TCL command to execute
timeout	integer	no	Optional command timeout in seconds

Source a .tcl script file in the Vivado session (uses source under the hood). Helpful for replaying canonical Red Pitaya / Xilinx reference scripts.

Parameter	Type	Required	Notes
path	string	yes	Absolute path to .tcl script
timeout	integer	no	Optional script timeout in seconds

Free

$0 forever

Every tool, no call limit
No card, and mcprush charges nothing for it
Source published under MIT
Runs on your machine — nothing of it reaches our gateway
Nothing to cap, because mcprush bills nothing

Nothing here is billable: mcprush charges nothing to install Vivado Red or to call it, at any volume.

ATrust score 93 / 100

Release 0.5.0 · scanned 3 Nov 2026

Two independent axes, because powerful and malicious are different questions. The grade is threat only. The capability level is blast radius, and it is never a penalty on the grade — it is priced as one subtract-only term in the score, where you can see it.

Threat score100

Client score93

Findings0 threat · 8 capability

Capabilityhigh

Coveragesource

Verificationrepo

Surface digeste86847a17c2d17d90176503048f124715949c9d189bceb4ddf12ed87db539e19

Score vectorthreat 100 → client 93

Term	Level	What it prices	Points
capability-exposure	high	capability blast radius (high) — client exposure if the model is manipulated	−6
verification-discount	repo	publisher verification (public source) — no provenance, but the source is public and inspectable	−1
coverage-honesty	source	inspection depth (source) — how much of the target the scan could see	−0

score = clamp(round(threatScore − E_cap − E_ver − E_cov), 0, 100). No model, no opinion, no network call at scoring time: the same methodology version against the same bytes always produces this number, and every line above is a field of the report rather than a summary of it.

What the scan could actually read

A grade is only as meaningful as its coverage, so the scanner publishes its own depth before it publishes its result.

Tool surfaceread

Implementation sourceread

Package metadataread

Live transportnot available

Tools were statically extracted from the published source (93 recovered), not enumerated from a running server. Tool-poisoning, Unicode-smuggling, capability and toxic-flow analysis ran on this inferred surface, but a mis-parsed registration could be missed or mis-attributed, so tool-derived findings are capped below “confirmed”. To grade the real runtime surface, scan the running server: --command "npx -y <package>".

Capability — what it could do if the model were manipulated

Tags derived from each tool’s schema and the implementation, not from what the tool calls itself. high is the level these add up to.

Tool	Capability tags	Why the tag was assigned
report_power	no tags
report_drc	no tags
report_methodology	no tags
report_qor_assessment	no tags
report_clock_interaction	no tags
get_timing_summary	no tags
get_timing_paths	no tags
get_utilization	no tags
get_clocks	no tags
get_messages	no tags
create_block_design	no tags
save_bd_design	no tags
close_bd_design	no tags
list_bd_cells	no tags
add_ip_to_bd	no tags
create_bd_port	no tags
add_module_to_bd	no tags
configure_bd_cell	no tags
connect_bd_net	no tags
connect_bd_intf_net	no tags
auto_connect_axi	no tags
apply_ps7_preset	no tags
validate_block_design	no tags
regenerate_bd_layout	no tags
assign_bd_address	no tags
generate_bd_wrapper	no tags
deploy_to_redpitaya	no tags
ssh_redpitaya_exec	code-exec	code-exec: keyword "exec" in tool name, parameter "command"
get_design_hierarchy	no tags
get_ports	no tags
get_nets	no tags
get_cells	no tags
get_vivado_doc	no tags
list_vivado_docs	no tags
request_feature	no tags
list_feature_requests	no tags
run_synthesis	no tags
run_implementation	no tags
generate_bitstream	no tags
set_run_strategy	no tags
open_hw_manager	no tags
close_hw_manager	no tags
connect_hw_server	no tags
refresh_hw_device	no tags
program_device	no tags
create_ip	no tags
configure_ip	no tags
generate_ip_target	no tags
synth_ip	no tags
upgrade_ip	no tags
report_ip_status	no tags
open_project	no tags
close_project	no tags
get_project_info	no tags
create_project	no tags
add_sources	no tags
add_constraints	no tags
list_boards	no tags
get_board_info	no tags
load_board_xdc	no tags
generate_cfgmem	no tags
get_synthesis_errors_parsed	no tags
create_redpitaya_project_rtl	no tags
rp_fetch_repo	untrusted-input	untrusted-input: keyword "fetch"
rp_setup_workspace	no tags
rp_list_projects	no tags
rp_workspace_info	no tags
rp_create_custom_project	no tags
rp_build_project	no tags
generate_full_report	no tags
read_report_section	no tags
start_session	no tags
stop_session	no tags
session_status	no tags
check_session_health	no tags
get_host_status	no tags
launch_simulation	no tags
run_simulation	no tags
restart_simulation	no tags
close_simulation	no tags
get_simulation_time	no tags
get_signal_value	no tags
get_signal_values	no tags
add_signals_to_wave	no tags
set_simulation_top	no tags
get_simulation_objects	no tags
get_scopes	no tags
step_simulation	no tags
add_breakpoint	no tags
remove_breakpoints	no tags
get_simulation_messages	no tags
run_tcl	code-exec	code-exec: parameter "command"
run_tcl_script	no tags

Toxic-flow graph

The lethal trifecta, checked as a graph rather than as a checklist: untrusted input, a sensitive source and an external sink have to meet before there is a path worth worrying about.

flow-1

Untrusted input can drive an external action even though no sensitive source is exposed.

Supply chain and provenance

Integrityfirst-seen

Surface digeste86847a17c2d17d9

Scanned2026-11-03

This is the first scan of this surface here, so there is nothing yet to compare it against.

Every result on this tab comes from one deterministic pass over the published package — offline, rule by rule, and auditable line by line above. Same methodology version, same bytes, same score.

Where are you running it?

Tool surface

Release history

Vivado Red MCP

What it does

Quickstart

Where are you running it?

Tool surface

What counts against your monthly calls

What the scan could actually read

Capability — what it could do if the model were manipulated

Toxic-flow graph

Supply chain and provenance

Release history

See also