Compiler-backed read-only Verilog and SystemVerilog project analysis.
Free
One server, in developer tools & repos. Compiler-backed read-only Verilog and SystemVerilog project analysis.
Developer Tools & Repos
1
server published
1 category
4k
downloads
counted by the registries
0
followers
told when a release lands
1 of 1
security-scanned
servers with a scan grade
1 MCP server, most downloaded first. 1 of 1 is free to start.
Authentication
0 of 1 use OAuth
The rest either hold an API key issued by the publisher or ask for nothing.
Support
Community publisher
Listed without a verification tick. Read the listing before installing.